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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:41:59 04/05/2008 
-- Design Name: 
-- Module Name:    VGAtiming - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity VGAtiming is
    Port ( VSync : out  STD_LOGIC;
           HSync : out  STD_LOGIC;
           Vaddr : out  STD_LOGIC_VECTOR (9 downto 0);
           Haddr : out  STD_LOGIC_VECTOR (9 downto 0);
			  Active : out  STD_LOGIC;
           clk : in  STD_LOGIC);
end VGAtiming;

architecture Behavioral of VGAtiming is

	signal HC0, VC0 : std_logic;
	signal HSyn, VSyn : std_logic := '1';
	signal HActive, VActive : std_logic;
	signal HSynStart : std_logic_vector(1 downto 0) := "00";
	signal VCount, HCount : std_logic_vector(9 downto 0) :=(others=>'0');
	signal LineNum, PixelNum : std_logic_vector(9 downto 0) :=(others=>'0');
	signal DivideByTwo : std_logic;
	
	type t_H is (s_HSyn, s_HFporch, s_HActive, s_HBporch);
	type t_V is (s_VSyn, s_VFporch, s_VActive, s_VBporch);
	signal h_state : t_H := s_HBporch;
	signal v_state : t_V := s_VBporch;

begin

	HC0 <= '1' when HCount = 0 else '0';
	VC0 <= '1' when VCount = 0 else '0';
	Haddr <= PixelNum(9 downto 0);
	Vaddr <= LineNum;
	HSync <= HSyn;
	VSync <= VSyn;
	Active <= HActive and VActive;

	Horizontal : process(clk, HC0, Vsyn) is
	begin   
      if rising_edge(clk) then
			
			DivideByTwo <= not DivideByTwo;
         HSynStart <= HSynStart(0) & HSyn;   
         
         if DivideByTwo = '1' then  
         
            HCount <= HCount-1;
				
            case h_state is
            
            when s_HSyn =>
               if HC0 = '1' then
                  HCount <= conv_std_logic_vector(95,HCount'length);
                  HSyn <= '1';
                  h_state <= s_HBporch;
               end if;
            when s_HBporch =>
					PixelNum <= (others=>'0');
               if HC0 = '1' then
                  HCount <= conv_std_logic_vector(639,HCount'length);
						HActive <= '1';
                  h_state <= S_HActive;
               end if;
            when s_Hactive =>
					PixelNum <= PixelNum+1;
               if HC0 = '1' then
                  HCount <= conv_std_logic_vector(47,HCount'length);
						HActive <= '0';
                  h_state <= s_HFporch;
               end if;
            when s_HFporch =>
               if HC0 = '1' then
                  HCount <= conv_std_logic_vector(15,HCount'length);
						HSyn <= '0';
                  h_state <= s_HSyn;
               end if;
                 
            end case;
         end if;
      end if; 
   end process; 
	
	Vertical : process(clk, VC0, HSynStart) is
   begin
      if rising_edge(clk) then
      
         if HSynStart = "01" then  
         
            VCount <= VCount-1;
            
            case v_state is
            
            when s_VSyn =>
               if VC0 = '1' then
                  VCount <= conv_std_logic_vector(30,VCount'length);
						VSyn <= '1';
                  v_state <= s_VBporch;
               end if;
            when s_VBporch =>
					LineNum <= (others=>'0');
               if VC0 = '1' then
                  VCount <= conv_std_logic_vector(479,VCount'length);
						VActive <= '1';
                  v_state <= s_VActive;
               end if;
            when s_Vactive =>
					LineNum <= LineNum+1;
               if VC0 = '1' then
                  VCount <= conv_std_logic_vector(10,VCount'length);
						VActive <= '0';
                  v_state <= s_VFporch;
               end if;
            when s_VFporch =>
               if VC0 = '1' then
                  VCount <= conv_std_logic_vector(1,VCount'length);
						VSyn <= '0';
                  v_state <= s_VSyn;
               end if;
				end case;
         end if;
         
      end if;
   end process;

end Behavioral;

